Commonly-assigned, copending U.S. patent application Ser. No. 09/469,454, entitled xe2x80x9cSelf-Aligned Silicon Carbide LMOSFETxe2x80x9d, filed Dec. 12, 1999.
Commonly-assigned, copending U.S. patent application Ser. No. 09/469,450, entitled xe2x80x9cSilicon Carbide N-Channel Power LMOSFETxe2x80x9d, FILED Dec. 12, 1999.
This invention relates to lateral metal-oxide-semiconductor field effect transistors (LMOSFETs) used in high-power applications such as UHF transmission which are especially suited for silicon carbide (SiC) technology. In particular, the invention relates to a SiC LMOSFET having a self-aligned gate structure with improved gate reach-through protection and methods of fabricating same.
In recent years, the use of silicon lateral double-diffused metal-oxide-semiconductor field effect transistors (Si LDMOSFETs) in high-power and high-frequency applications has increased enormously. This is because Si LDMOSFETs offer simpler gate drive and faster response than bipolar devices.
Si LDMOSFETs are typically fabricated using self-aligned techniques, which minimize gate overlap of the source and drift/drain regions. Minimal overlap is critical for maintaining low gate-to-source and gate-to-drift/drain capacitances, which can adversely affect the high frequency performance of the device. It is also desirable to reduce the overlap to decrease the cell pitch and conserve the silicon area used by the device.
Silicon carbide (SiC) is an attractive semiconductor material for high frequency and high power applications. The properties which make SiC attractive for high power UHF applications are its large critical electric field (10 times that of Si) and its large electron saturation velocity (2 times that of Si). The large critical electric field helps increase the breakdown voltage of the device and the large saturation velocity helps increase the peak current.
FIG. 1 shows an LMOSFET 10 as disclosed in commonly-assigned copending U.S. patent application Ser. No. 09/469,454 entitled xe2x80x9cSelf-Aligned Silicon Carbide LMOSFETxe2x80x9d. This SiC LMOSFET includes a self-aligned gate structure and offers protection against gate reach through. The LMOSFET 10 of FIG. 1 includes highly n-doped source and drain regions 11, 12, a lightly n-doped drift region 13 formed by an N- epitaxial layer 14, and an electrically insulated self-aligned gate structure 15 comprised of a gate oxide 16 and a gate metal 17, formed on a lightly-doped p-type SiC epitaxial layer 18 (P-epilayer). The gate structure 15 has edges 19 which are substantially aligned with the edges 20 of the source and drift regions 11, 13. Accordingly, the gate-to-source and gate-to-drift region overlap can be advantageously controlled by the thickness of the gate metal 17, which can be selected to be very small. A channel region 21 in the P- epilayer 18. The channel region 21changes from p-type to n-type due to inversion when a positive voltage greater than the threshold voltage of the LMOSFET 10 is applied to the gate 15 thereby providing a low resistance current path between the source region 11 and drift extension 13 of the drain region 12.
The LMOSFET 10 of FIG. 1 should provide many advantages in terms of better linearity, efficiency and power density at comparable frequencies, and higher frequency operation than Si LDMOSFETs. However, this LMOSFET may suffer from higher forward voltage drop, i.e., higher xe2x80x9con-resistancexe2x80x9d due to the fact that the current at the source side has to flow around a corner 22 where the gate oxide 16 has a greater thickness. The greater oxide thickness results in a higher resistivity portion in inversion, which will likely result in higher forward voltage drop.
Therefore, a SiC LMOSFET is needed which overcomes the above problem.
Summarily described is an LMOSFET having a self-aligned gate with gate reach-through protection and method for making same. The LMOSFET comprises a first layer of SiC semiconductor material having a p-type conductivity and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. An etched trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer so that the source and drain regions are substantially lateral thereto. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material thereby forming a gate structure. A channel region is defined in the first layer beneath the gate structure. The source comer of the gate structure is either rounded or surrounded by the source region to provide a current path in the channel region which avoids sharp corners. Electrical contacts associated with the source and drain regions, and the gate structure establish source, drain, and gate electrodes.